Globalfoundries demonstrates 2.5D package for 14nm and 7nm finfet
- Author:Ella Cai
- Release on:2017-08-10
Globalfoundries (GloFo) has demonstrated silicon functionality of a 2.5D package for its high-performance 14nm finfet FX-14 integrated design system for ASICs.
The 2.5D ASIC package has a stitched interposer capability to overcome lithography limitations and a two terabits per second (2Tbps) multi-lane HBM2 PHY, developed in partnership with Rambus.
“With the advances in interconnect and packaging technology that has occurred in recent years, the line between wafer processing and packaging has blurred,” says GloFo’s Kevin O’Buckley. “Incorporating 2.5D packaging into ASIC design boosts performance beyond scaling and is a natural evolution of our capabilities. It enables us to support our customers in a one-stop end-to-end fashion, from product design through manufacturing and testing.”
The Rambus memory PHY is aimed at high-end networking and datacentre applications performing data-intensive tasks in systems requiring low latency and high-bandwidth. The PHY is compliant with the JEDEC JESD235 HBM2 standard, supporting data rates up to 2Gbps per data pin, enabling a total bandwidth of 2Tbps.It will also be used for the company’s 7nm Finfet process.
The 2.5D ASIC package has a stitched interposer capability to overcome lithography limitations and a two terabits per second (2Tbps) multi-lane HBM2 PHY, developed in partnership with Rambus.
“With the advances in interconnect and packaging technology that has occurred in recent years, the line between wafer processing and packaging has blurred,” says GloFo’s Kevin O’Buckley. “Incorporating 2.5D packaging into ASIC design boosts performance beyond scaling and is a natural evolution of our capabilities. It enables us to support our customers in a one-stop end-to-end fashion, from product design through manufacturing and testing.”
The Rambus memory PHY is aimed at high-end networking and datacentre applications performing data-intensive tasks in systems requiring low latency and high-bandwidth. The PHY is compliant with the JEDEC JESD235 HBM2 standard, supporting data rates up to 2Gbps per data pin, enabling a total bandwidth of 2Tbps.It will also be used for the company’s 7nm Finfet process.
