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Home > News > Company News > EDA embraces standard to strea.....

EDA embraces standard to streamline IC test and verification

  • Author:Ella Cai
  • Release on:2018-07-09
Caroline Hayes finds out about the Accellera effect at DAC 2018

As well as EDA, IP and SoC companies, this year’s DAC was distinguished by the number of industry bodies that were promoting their particular brand of technology and establishing standards which the industry should follow.

Accellera , the body promoting system level design, modelling and verification standards, was linked to several of the industry’s leading companies, with announcements around EDA and IP standards.

Accellera’s mission is to provide a platform language to improve design and verification and productivity of electronics products, said Lu Dai, senior director of engineering at Qualcomm and Accellera chair at the announcement of the Portable Test and Stimulus Standard (PSS)1.0 which had been approved by the organisation.

The specification – available for free download – allows user to specify verification intent and behaviours once and use them across multiple implementations and platforms.

The new standard is available immediately to download for free.

A single representation of stimulus and test scenarios for SoC test and coverage metrics for hardware and software verification can be used by many users across different levels of integration and under different configurations to generate simulation, emulation, FPGA prototyping and post-silicon implementations.

Dai believes the standard will have a “profound impact” on the industry, as it shifts the focus from system-level verification and increases designers’ productivity by being able to use one test specification which is portable across multiple platforms for design and verification.

The standard defines a domain-specific language and accompanying semantically-equivalent C++ class declarations, and creates a single representation of stimulus and test scenarios based on object-oriented programming languages, hardware-verification languages and behavioural modelling languages. The result can be used by the entire design team, from verification, test and design disciplines, and under different configurations and select the best tools from different suppliers for verification requirements. The standard uses native constructs for data flow, concurrency and synchronisation, resource requirements and states and transitions.

At DAC, Cadence announced that its Perspec System Verifier design tool supports the Portable Test and Stimulus standard. Part of the Verifier suite of tools, it automates automotive, mobile and server SoC coverage closures, and is also claimed to improve system-level test productivity by a factor of 10.

The Perspec System Verifier provides an abstract model-based approach for defining the SoC use cases from the PSS model and uses Unified Modeling Language (UML) activity diagrams to visualise the generated tests.

The Perspec System Verifier tests are optimised for each tool in the Verification Suite, including Cadence Xcelium Parallel Logic Simulation, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-based prototyping platform.  The tool also integrates with the company’s vManager Metric-Driven Signoff platform to support the new use-case coverage in the PSS. It generates tests that can use Verification IP (VIP), so that the verification content can be re-used via the PSS methodology, to accelerate SoC verification.

Another company supporting the PSS is Mentor. The company its upcoming release of the Questa inFact tool will support the standard. (The company donated its Questa inFact technology to the organisation in 2014 and it is the basis of the standard, claims the company.)

It believes that the PSS will increase the adoption portable stimulus into broader, mainstream use and help IC engineers efficiently collaborate in the design of products for new and emerging markets, such as artificial intelligence (AI), 5G wireless communication and autonomous driving.

Questa inFact uses machine learning and data mining techniques to increase productivity by up to a factor of 40, says Mentor, and across multiple phases of IC development. Designers can complete performance and power analysis at the IC level, verification engineers can achieve higher levels of coverage in less time, while validation engineers can fully integrate hardware and software, and test engineers can analyse and optimise their regression test environments, explained Mark Olen, product marketing group manager, Mentor IC Verification Solutions division.

The company has been refining the tool to comply with PSS as it evolved and has added applied classification machine learning to its graph-based Questa inFact technology to enable the targeting of scenarios not yet verified. This speeds up meeting coverage goals at the IP block level, and increases usefulness of bare metal testing at the IC level. The tool learns from each subsequent scenario during simulation or emulation.

The application of data mining technology extends the application of portable stimulus beyond verification. It enables the tool to collect and correlate transaction-level activity to characterise IC design performance parameters, such as fabric routing efficiency and bandwidth, system-level latency, cache coherency, arbitration efficiency, out-of-order execution, and opcode performance. It can also analyse and optimise regression test environments, to avoid the need for simulation and emulation cycles.

The tool can be used to generate UVM SystemVerilog test scenarios for functional coverage at the IP block level with the Questa simulator, and then re-use the test scenarios to generate C/C++ tests for traffic generation at IC level verification with the company’s Veloce emulator. It can also be used to generate assembly code at the system level for instruction-set verification and C/C++ scenarios for architectural exploration with the Vista virtual prototyping system. When used with Mentor’s Catapult High-Level Synthesis toolset it can generating C/C++ scenarios before, and RTL tests after, behavioural synthesis.