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Home > News > Industry News > 64th IEDM takes shape

64th IEDM takes shape

  • Author:Ella Cai
  • Release on:2018-08-15
The theme of  the 64th  IEEE International Electron Devices Meeting (IEDM) is “Device Breakthroughs from Quantum to 5G and Beyond”.

The meeting will be held from December 1-5 2018 is at the Hilton San Francisco Union Square hotel.

The progress on EUV will interest many.

“In terms of industrial applications, the evening panel session on EUV will give attendees the opportunity to explore and debate this emerging technology with the very people who are driving it forward,” says Rihito Kuroda, Publicity Vice Chair and Associate Professor at Tohoku University.

Focus Sessions

  • Quantum Computing – Quantum computing will enable new types of algorithms to tackle problems in areas from materials science to medicine to artificial intelligence. We are still in early stages, facing fundamental questions such as: What is the best way to implement a quantum bit of information? How to connect them together? How to scale to larger systems without being overwhelmed by errors? This session brings together experts at the forefront of quantum computing research. Starting from an applications perspective, attendees will hear about different approaches to address fundamental questions at the device level; the progress achieved so far; and next steps. 
    • Application Requirements for Quantum Computing, John Preskill, Caltech 
    • Materials and Device Challenges for Near-Term Superconducting Quantum Processors, Jerry Chow, IBM 
    • Towards Scalable Silicon Quantum Computing, Maud Vinet, CEA-Leti 
    • Silicon Isotope Technology for Quantum Computing, Kohei Itoh, Keio University 
    • Qubit Device Integration Using Advanced Semiconductor Manufacturing Process Technology, Ravi Pillarrisetty, Intel 
    • Scalable Quantum Computing with Single Dopant Atoms in Silicon, Andrea Morello, Univ. New South Wales 
    • Majorana Qubits, Leo Kouwenhoeven, Microsoft 

  • Future Technologies Towards Wireless Communications: 5G and Beyond – 5G technology will drastically reduce limitations on accessibility, bandwidth, performance, and latency, but as it triggers fundamentally new applications it also will impose unique hardware requirements. This focus session will set a big picture view and then narrow down to how innovations in CMOS technologies, devices, filters, transceivers and antennas are coming together to enable the 5G platform. 
    • Intel 22nm FinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit Design Optimization for FinFET Technology, Hyung-Jin Lee, Intel 
    • RFIC/CMOS Technologies for 5G, mmWave and Beyond, Ali Niknejad, UC Berkeley 
    • GaN HEMTs for 5G Base Station Applications, Shigeru Nakajima, Sumitomo Electron Devices 
    • Highly Integrated mm-Wave Transceivers for Communication Systems, Vadim Issakov, Infineon 
    • BAW Filters for 5G Bands, Robert Aigner, Qorvo 
    • Reconfigurable Micro/Millimeter-wave Filters, Dimitrios Peroulis, Purdue 

  • Challenges for Wide Bandgap Device Adoption in Power Electronics – Wide bandgap (WBG) power devices offer potential savings in both energy and cost. But converters powered by WBG devices require innovation at all levels, entailing changes to system design, circuit architecture, qualification metrics and even market models. Can SiC or GaN push beyond what silicon can possibly achieve? What are the big challenges researchers should answer over the next decade? A team of experts will interpret the landscape and discuss challenges to the widespread adoption of these technologies. 
    • GaN and SiC Devices for Automotive Applications, Tetsu Kachi, Nagoya University 
    • SiC MOSFET for Mainstream Adoption, Peter Friedrichs, Infineon 
    • GaN Power Commercialization with Highest Quality-Highest Reliability 650V HEMTs- Requirements, Successes and Challenges, Primit Parikh, Transphorm 
    • The Current Status and Future Prospects of SiC High Voltage Technology, Andrei Mihaila, ABB 
    • Barriers to Wide Bandgap Semiconductor Device Adoption in Power Electronics, Isik Kizilyalli, ARPA-E 
    • High to Ultra-High Voltage SiC Power Device Technology, Yoshiyuki Yonezawa, AIST 
    • Effects of Basal Plane Dislocations on SiC Power Device Reliability, Robert E. Stahlbush, Naval Research Laboratory 

  • Interconnects to Enable Continued Technology Scaling – BEOL copper (Cu) interconnects are close to end-of-life as a manufacturing technology, while the increasing complexity of MEOL processes requires novel materials. Also, the end of the Cu roadmap will coincide with significant changes in the dominant transistor architecture, and therefore the interaction between transistor architecture and interconnect will drive future interconnect development. This session provides a holistic perspective of interconnect scaling challenges and solutions. It will address the drivers of future interconnect architectures, the process options likely to be implemented in manufacturing, and how they will be tuned to ensure circuit reliability is maintained. 
    • Interconnect Design and Technology Optimization for Conventional and Exotic Nanoscale Devices: A Physical Design Perspective, A. Naeemi, Georgia Tech 
    • Mechanisms of Electromigration Damage in Cu Interconnects, C. K. Hu, IBM 

    • Interconnect Metals Beyond Copper: Reliability Challenges and Opportunities, K. Croes, Imec 
    • Microstructure Evolution and Effect on Resistivity for Cu Nano-interconnects and Beyond, Paul Ho, UT Austin 
    • Integrating Graphene into Future Generations of BEOL Interconnects, H.-S. Philip Wong, Stanford 
    • Interconnect Trends for Single Digit Nodes, Mehul Naik, Applied Materials 

90-Minute TutorialsSaturday, Dec. 1

A series of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research.

  • Reliability Challenges in Advanced Technologies, Ryan Lu, TSMC 
  • STT-MRAM Design and Device Requirements, Shinichiro Shiratake, Toshiba Memory 
  • Quantum Computing Primer, Mark B. Ritter, IBM 
  • Power Transistors in Integrated BCD Technologies,  Hal Edwards, Texas Instruments 
  • Design-Technology Co-optimization at RF and mmWave, Bertand Parvais, IMEC 
  • Emerging Device Technologies for Neuromorphic Computing, Damien Querlioz, CNRS 

Short Courses – Sunday, Dec. 2

Full-day Short Courses will be held, offering the opportunity to learn about important areas and developments, and to network with experts from around the world.

  • It’s All About Memory, Not Logic!, organized by Nirmal Ramaswamy, Micron 
  • DRAM: Its Challenging History and Future, Dong Soo Woo, Samsung 
  • 3D Flash Memories: Overview of Cell Structures, Operations and Scaling Challenges, Makoto Fujiwara, Toshiba Memory Corporation. 
  • Emerging Memories Including Cross-Point, Opportunities and Challenges, Kiran Pangal, Intel 
  • Memory Reliability, Qualification and their Relation to System-Level Reliability Strategies, Todd Marquart, Micron 
  • Packaging Technology for High Bandwidth Memory, Nick (Namseog) Kim, SK Hynix 
  • Processing in Memory (PIM): Performance and Thermal Challenges and Opportunities, Mircea Stan, UVA 

  • Scaling Survival Guide in the More-than-Moore Era, organized by Jin Cai, TSMC 
  • Extreme-UV Lithography – Principles, Present Status and Outlook, Tony Yen, ASML 
  • MOSFET Scaling Knobs (GAA, NCFET…) and Future Alternatives, Witek Maszara, Globalfoundries 
  • Overcoming Variation Challenges, Sivakumar Mudanai, Intel 
  • Embedded Memory: Present Status and Emerging Architecture and Technology for Future Applications,Eric Wang, TSMC 
  • 3D Integration for Density and Functionality, Julien Ryckaert, Imec 
  • Advanced Packaging: the Next Frontier for Moore’s “Law,” Subramanian Iyer, UCLA 

Plenary Presentations – Monday, Dec. 3

  • Future Computing Hardware for AI, Jeffery Welser, Vice President, IBM Research-Almaden 
  • “4th Industrial Revolution and Foundry: Challenges and Opportunities,” Eun Seung Jung, President of Foundry Business, Samsung Electronics 
  • The Status, Challenges and Opportunities of 5G, Prof. Gerhard P. Fettweis, TU Dresden 

Evening Panel Session – Tuesday evening, Dec. 4

  • EUV: Too Little, Too Late, Too Expensive or the Ultimate Cure-All?, organized by Sanjay Natarajan, Senior VP of Applied Materials. Much progress has been made in EUV patterning technology, and yet manufacturing throughput, masks, pellicles and resists still persist as problems today. The complexity of reliably transferring features at the 7nm node and below using quadruple patterning and 193nm immersion is affecting yield, affecting the cost-per-gate reduction and slowing down Moore’s Law. The industry eagerly awaits EUV, but is it too little, too late and too expensive, or is it the ultimate panacea? A team of world-renowned experts from the leading logic and memory IDMs, foundries and fabless companies will vigorously debate the issue. 

Luncheon – Wednesday, Dec. 5

The speakers are yet to be determined, but IEDM will have a new lunch event this year that features industry leaders engaging the audience on the state of the industry, and on careers in device and VLSI technology.

Vendor Exhibition/Poster Sessions

  • A vendor exhibition will be held once again, with special exhibit events in the evenings. 
  • This year two poster sessions will be held, one on MRAM technology organized by the IEEE Magnetics Society, the other a student research showcase hosted by the Semiconductor Research Corporation