Low phase noise 55MHz-15GHz fractional-N synth
- 저자:Ella Cai
- 에 출시:2018-07-20
ADI’s ADF5610 fractional-N synthesiser covers 55MHz to 15GHz, and is claimed to have “industry’s lowest phase noise performance on a single chip” by its maker.
Fabbed on a SiGe BiCMOS process, at 10GHz VCO phase noise is -114dBc/Hz at 100kHz offset and -165dBc/Hz at 100MHz offset. Normalized phase noise floor is -229dBc/Hz.
Typical output power is 6dBm.
With the appropriate loop filter, according to ADI, the on-die PLL can hop and lock in <50μs, and phase detector spurious levels are typically below -45dBc.
Various 3.3V and 5V power supplies are needed, supplied from low noise, high PSRR (power supply rejection ratio) regulators to maintain performance.
For power saving, the synthesiser can be shut-down via hardware or software, and logic inputs have 1.8 V and 3.3 V modes. Programming is though an SPI interface.
Diverse applications are expected, including in aerospace, defense, wireless infrastructure, microwave point-to-point links, test equipment, in measurement and in satellite terminals.
Design support comes from an evaluation module and the firm’s ADIsimPLL synthesiser design and simulation tool, which assesses phase noise, lock time and jitter.
ADF5610
Fabbed on a SiGe BiCMOS process, at 10GHz VCO phase noise is -114dBc/Hz at 100kHz offset and -165dBc/Hz at 100MHz offset. Normalized phase noise floor is -229dBc/Hz.
Typical output power is 6dBm.
With the appropriate loop filter, according to ADI, the on-die PLL can hop and lock in <50μs, and phase detector spurious levels are typically below -45dBc.
Various 3.3V and 5V power supplies are needed, supplied from low noise, high PSRR (power supply rejection ratio) regulators to maintain performance.
For power saving, the synthesiser can be shut-down via hardware or software, and logic inputs have 1.8 V and 3.3 V modes. Programming is though an SPI interface.
Diverse applications are expected, including in aerospace, defense, wireless infrastructure, microwave point-to-point links, test equipment, in measurement and in satellite terminals.
Design support comes from an evaluation module and the firm’s ADIsimPLL synthesiser design and simulation tool, which assesses phase noise, lock time and jitter.
ADF5610
- 55MHz to 15GHz
- 100MHz max phase detector rate
- -115dBc/Hz typ at 100kHz (7GHz) phase noise
- -114dBc/Hz typ at 100kHz (10GHz) phase noise
- -110dBc/Hz max at 100kHz (15GHz) phase noise
- +5dBm rf out
- -229 integer
- -226dBc/Hz fractional
- 24bit step size, 3Hz typ resolution
- Exact frequency mode with 0Hz error
- -40 to +85°C
- 48lead, 7x7mm LFCSP
