Broadcom plans 7nm tape-outs this quarter
- 著者:Ella Cai
- 公開：:2017-11-23
Broadcom has announced silicon-proven 7nm IP and says it will tape out its first 7nm designs this quarter.
The IP targets deep learning and networking applications. Based on TSMC 7nm process technology, the platform offers IP cores including SerDes, HBM PHY, Die2Die PHY, mixed-signal IP, and foundation IP such as standard cells, SRAM, TCAM memory, and I/O cells.
According to the company its SerDes portfolio includes 112G PAM-4, 58G PAM-4, 32G and 16G Gen4 SerDes. Its JEDEC-compliant HBM Gen2 and HBM Gen3 PHY provide a high bandwidth memory interface upgrade path for next generation deep learning, routing and high performance computing (HPC) ASICs.
It has a comprehensive portfolio of Arm cores and peripherals, comprehensive single port, multi-port, register file and TCAM memory compilers and optimised standard cell libraries. Die2Die PHY enables multi-die integration, logic and I/O disaggregation, reports Broadcom.
CoWoS packaging combined with HBM2/3 PHY enables high bandwidth memory interface for next generation training in deep learning, HPC and routing applications.
High-bandwidth, low-footprint SerDes cores (112G and 56G SerDes) enable high port density for switching and routing applications and high bandwidth inter-node connections in deep learning and HPC applications.
The design kit for 7nm ASIC platform is available now. Several customer products are already in development. Lead 7nm customer ASIC products are scheduled to tape-out in the last quarter of 2017.
The IP targets deep learning and networking applications. Based on TSMC 7nm process technology, the platform offers IP cores including SerDes, HBM PHY, Die2Die PHY, mixed-signal IP, and foundation IP such as standard cells, SRAM, TCAM memory, and I/O cells.
According to the company its SerDes portfolio includes 112G PAM-4, 58G PAM-4, 32G and 16G Gen4 SerDes. Its JEDEC-compliant HBM Gen2 and HBM Gen3 PHY provide a high bandwidth memory interface upgrade path for next generation deep learning, routing and high performance computing (HPC) ASICs.
It has a comprehensive portfolio of Arm cores and peripherals, comprehensive single port, multi-port, register file and TCAM memory compilers and optimised standard cell libraries. Die2Die PHY enables multi-die integration, logic and I/O disaggregation, reports Broadcom.
CoWoS packaging combined with HBM2/3 PHY enables high bandwidth memory interface for next generation training in deep learning, HPC and routing applications.
High-bandwidth, low-footprint SerDes cores (112G and 56G SerDes) enable high port density for switching and routing applications and high bandwidth inter-node connections in deep learning and HPC applications.
The design kit for 7nm ASIC platform is available now. Several customer products are already in development. Lead 7nm customer ASIC products are scheduled to tape-out in the last quarter of 2017.
